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X9470
Figure 1. Typical Application
A2
INC/DEC
RW REF RH REF RL REF
R REF
AGND
V OUT
V+
V DD
V SENSE+
C BULK
A1
A0
Comparator
V REF
VP
Instrumentation
Amplifier
? V
V SENSE–
R SENSE
SDA
I2C
interface
VREF
control
choke
SCL
Control &
Status Registers
Vbias
control
R BIAS
+
–
V BIAS
FILTER
RF
out
RF PA in
EEPROM
Matching
RF Impedance
VCC
VSS
CS
RH BIAS RW BIAS RL BIAS
SHDN
Class A Example
X9470 FUNCTIONAL DESCRIPTION
This section provides detail description of the following:
– Sense and Scale Block Description
– Bias Adjustment Control Block Description
– Output Block Description
– Bias Adjustment and Storage Description
SENSE AND SCALE BLOCK
The Sense and Scale Circuit Block (Figure 2) imple-
ments an instrumentation amplifier whose inputs
(V SENSE+ and V SENSE- ) are across an external sense
resistor in the drain circuit of an RF Power FET. V SENSE+
is connected to V DD , the drain voltage source for the RF
power FET, and V SENSE- pin is connected to the other
end the external sense resistor.
An internal instrumentation amplifier (IA) will sense the
? V and amplify it by a gain factor of K 1 (see Equation
1). The resulting output is compared with V REF at the
comparator. V REF can be a fixed reference voltage or
adjusted by using the 64-tap digital potentiometer. The
output of the comparator is used to increment or dec-
rement the R BIAS potentiometer in the Bias Adjust-
ment Circuit Block. The gain factor K 1 is designed
such that the Sense and Scale Block will set the Bias
Adjustment Circuit Block to operate in a given voltage
range (mV) vs. drain current adjustment (mA).
The output of the IA is also available at the pin Vout to
enable drain current monitoring. The gain at Vout is
fixed at a factor of K 2 , lower than K 1 so that high I DQ
currents will not cause saturation of the Vout signal.
The equation for Vout is given as:
? V = I DQ * R SENSE
V OUT = K 2 * ? V
K 2 is fixed to 20x for the Vout pin
BIAS ADJUSTMENT CIRCUIT BLOCK
There are three sections of this block (Figure 3): the
input control, counter and decode section (1), the
resistor array (2); and the non-volatile register (3). The
input control section operates just like an up/down
counter. The input of the counter is driven from the
output of the comparator in the Sense and Scale Block
and is clocked by the SCL signal. The output of this
counter is decoded to select one of the taps of a 256-
tap digital potentiometer.
I DQ ?
V REF
K 1 * R SENSE
(1)
K 1 is fixed 50x for the internal comparator input.
12
FN8204.0
March 8, 2005
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